Non-volatile ferroelectric RAM, commonly referred to as FeRAM or FRAM devices and other types of semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. FeRAM cells employ a ferroelectric capacitor (FeCap) including a pair of capacitor plates with a ferroelectric material, such as SBT or PZT, serving as the capacitor dielectric situated between them. Ferroelectric materials have two different stable polarization states that may be used to store binary information, where the ferroelectric behaviour follows a hysteresis curve of polarization versus applied voltage. FeRAM memory cells are non-volatile memory devices, because the polarization state of a FeCap remains when power is removed from the device.
Two types of memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (a 1T/1C or 1C memory cell) requires less silicon area, thereby increasing the potential density of the memory array, but is less immune to noise, process and cycling variations. Additionally, a 1C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2T/2C or 2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2C memory cell generally is more stable than a 1C memory cell.
As illustrated in prior art FIGS. 1A and 1B, a 1T/1C FeRAM cell 100 includes one transistor (also called pass or pass gate transistor) 112 and one ferroelectric storage capacitor 114. The storage capacitor 114 is connected to a source terminal 115 of the transistor 112. The 1T/1C cell 100 is read from by applying an X-axis or word line WL signal to the gate 116 of the transistor, thereby connecting the FeCap 114 to the drain of the transistor at the bit line BL 118. A pulse signal is then applied to the plate line PL 120.
The charge on the bit line 118 of the transistor 112 is, therefore, the FeCAP capacitor charge shared with the bit line capacitance and the potential on the bit line is the charge on the bit line divided by the bit line capacitance. Since the FeCAP capacitor charge is dependent upon the bi-stable polarization state of the ferroelectric material, the bit line potential can have two distinct values. A sense amplifier (see FIG. 3) is connected to the bit line 118 and detects the voltage at a storage node SN 125 of storage capacitor 114 associated with a logic or polarization value of either 1 or 0 of the FeCAP. Frequently, the sense amplifier reference voltage is provided by a “reference cell” (not shown), which comprises a ferroelectric or non-ferroelectric capacitor connected to another bit line that is not being read. In this manner, the memory cell data is retrieved.
As illustrated, for example, in prior art FIG. 1B, a 2T2C memory cell 130 in a memory array couples to a bit line 132 and its complimentary bit line-bar 134 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The 2T2C ferroelectric memory cell comprises two transistors 136 and 138 and two ferroelectric capacitors 140 and 142, respectively. The first transistor 136 couples between the bit line 132 and a first capacitor 140, and the second transistor 138 couples between the bit line-bar 134 and the second capacitor 142. The first and second capacitors 140 and 142 have a common terminal or plate (the plate line PL) 144 to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 136 and 138 of the 2T2C ferroelectric memory cell 130 are enabled (e.g., via their respective word line 146) to couple the capacitors 140 and 142 to the complementary logic levels on the bit line 132 and the bit line-bar line 134 corresponding to a logic state to be stored in memory. The plate line common terminal 144 of the capacitors is pulsed during a write operation to polarize the 2T2C memory cell 130 to one of the two logic states (a ZERO or ONE).
In a read operation, the first and second transistors 136 and 138 of the 2T2C memory cell 130 are enabled via the word line 146 and the plate line is pulsed (pulse sensing) or stepped to the supply voltage Vdd (step sensing) to couple the information stored on the first and second capacitors 140 and 142 to the bit line 132 and the bit line-bar line 134, respectively. A differential signal (not shown) is thus generated across the bit line 132 and the bit line-bar line 134 by the 2T2C memory cell 130. A sense amplifier (not shown) that provides a signal corresponding to the logic level stored in memory senses the differential signal.
Several additional memory devices have been developed utilizing FeCaps, such as the four transistor (4T) two capacitor (2C) non-volatile (NV) SRAM cell (4T/2C NV SRAM), and the FeCap based reference cell noted above.
Feature sizes of integrated circuits are continuously decreasing in order to increase the packing density and operating speed of the various semiconductor devices formed thereby. As feature sizes continue to shrink, however, the resistance of various metal lines and interconnects also increase that may induce conductive noise problems, particularly at high signal transition rates. Accordingly, although FeRAM arrays provide a near ideal NVM memory storage mechanism, as scaling trends continue, increased data error rates may also be observed in FeRAM devices, particularly at fast memory cycle times.
In addition, with these scaling trends, one semiconductor fabricating process that experiences unique challenges is photolithography. Photolithography involves selectively exposing regions of a resist-coated silicon wafer utilizing a reticle (often called a mask) that includes a pattern thereon corresponding to features to be formed in a layer on the substrate.
It is well known in the art of photolithography that light passing through the reticle is refracted and scattered by the edges of the chrome mask patterns of the reticle, causing the projected image to exhibit some rounding and other forms of optical distortion. These optical distortions can increase the maximum resistance of a metal line and may cause an increase of data error rate. As feature scaling trends continue, variations of feature critical dimensions may no longer be ignored in present day circuit layouts. The problem highlighted above becomes even more pronounced in integrated circuit designs having submicron feature sizes near the wavelength of the radiation employed in the photolithographic process.
In addition, the diffraction and scattering of the radiation in the distorted illumination pattern propagates through the developed resist pattern and negatively impacts the integrated circuit features, such as polysilicon gate regions, vias in dielectrics, etc. As a result, integrated circuit performance is often degraded.
To mitigate this problem, a reticle correction technique known as optical proximity correction (OPC) has been developed and applied to portions of a reticle to mitigate the distorting effects of diffraction and scattering.
Various corrections or modifications are made to the base features of the design layout to compensate for the optical distortions produced by the imaging effects. In addition, variations in the photoresist and other such imaging material processing cause damage to the features as fabricated, and degradations from the layout design add to the CD variation and failure rate of a targeted CD for a feature. Imaging material processing is complex and difficult to model in OPC designs. Further, other post patterning processes such as etch and cleaning operations are equally difficult to model in OPC designs and cause substantial CD variation of the desired features.
Because these difficulties may persist in the best of OPC models and such methods may not provide adequate correction for the various processes, dummy rows and columns of repeating features are often beneficially used around the edges or boundary of the core region of memory arrays. Dummy rows and dummy columns placed at the edges of memory arrays help maintain the same pattern uniformity as the adjacent interior rows and columns of array features or elements. For a typical memory array, a dummy row may comprise a dummy wordline and plate line as well as the associated dummy memory cells and select circuits, while a dummy column may comprise a dummy bit line (or a pair of dummy bit lines) as well as the associated sense amplifier circuit and dummy memory cells. During memory array operations, dummy rows and columns are typically deactivated, as these dummy elements usually do not represent the operational characteristics of the interior or core region rows and columns of the array.
In spite of using dummy columns and rows and utilizing special OPC design considerations in the manufacture of semiconductor devices, there is a need for an improved FeRAM array that provides a reduced data error rate, particularly at fast memory cycle times.